The present invention disclosed herein relates to a delay locked loop and method of generating a clock, and more particularly, to a delay locked loop that shifts the phase of a reference clock signal or corrects a duty cycle, and to a method of generating a clock phase-shifted from the reference clock signal or having a corrected duty cycle.
A delay locked loop (DLL) performs an operation of synchronizing the phase of an output clock with a reference clock. In general, the DLL may be used to generate an output clock phase-synchronized with the reference clock in an electronic device such as a semiconductor memory. A DLL circuit may be used for generating a timing signal for the operation of e.g., dynamic random access memory (DRAM), namely, a data sampling signal used when outputting data from a semiconductor memory device or when storing data in a semiconductor memory device.
The DLL which generates an output clock phase-shifted by 90° from an input clock for data sampling is used at the receiving unit of a memory interface. A phase shift DLL performs data sampling by using a clock 90° phase-shifted from the input clock. A main performance parameter of the phase shift DLL needed for obtaining a high data rate is phase shift accuracy and duty cycle correction.
A typical DLL performs 90° phase shift by using a plurality of delay lines. The typical DLL generates 90°, 180°, 270° and 360° phase-shifted clocks by using e.g., four delay lines. However, when controlling each delay line by using the same control code, it is difficult to obtain accurate phase shift due to a mismatch between delay lines and there is a limitation in that a phase shift error occurs.
It might also be considered to adjust a control code for each of the delay lines. In this case, the control codes of delay lines are independently determined so that each of the delay lines generates a delay corresponding to a ¼ cycle. However, since a controller must exist for each delay line independently, such a DLL has a limitation in that design complexity increases. Also, there are limitations in that a plurality of delay lines is needed and an area and power consumption increase.
On the other hand, when an output clock having an accurate duty cycle is used for data sampling, it is possible to decrease an error in data transmission and it is possible to increase a data rate. In the case of a semiconductor memory device, a signal timing margin may be maximized when the duty cycle of an output clock is maintained at 50%. When data is sampled by using an output clock of the duty cycle departs from 50%, a timing margin decreases and a bandwidth decreases, so it may be difficult to perform data sampling at an accurate timing.
However, due to factors such as a characteristic of an external jitter and non-uniform delay values of internal delay elements, the duty cycle of the output clock of a DLL frequently departs from 50%. As such, when there is a distortion of a duty cycle, there may be a setup/hold time violation in a flip-flop used as a register in a memory.
Thus, the DLL further employs an additional duty cycle correction (DCC) circuit to perform the correction of a duty cycle. In particular, in the case of a semiconductor memory sensitive to the duty cycle of a clock, such as a double data rate (DDR) memory that uses the falling edge of the clock as well as the rising edge thereof for data sampling, it is almost essential to incorporate the DCC circuit into the DLL.
A typical DCC circuit uses a plurality of delay lines to generate signals phase-delayed differently from a reference clock and uses signals having phase differences (such as signals having 90° and 270° phase differences with respect to the reference clock) to perform duty correction for obtaining a 50% duty cycle. However, due to a process variation, the delay time of each delay line may irregularly vary. Due to the mismatch between delay lines, the accuracy of duty cycle correction is not accurately ensured. Moreover, with the recent micro manufacturing process, the effect of a process variation increases and thus an error in duty cycle due to the mismatch between delay lines increases. In addition, since the typical DCC circuit is separately incorporated into the DLL in addition to delay lines to perform an operation of correcting a duty cycle, there are limitations in that the size of the DLL becomes large due to the DCC circuit and power consumption also increases.